For 19 years GSA (going back to the days when it was Fabless Semiconductor Association, FSA) has recognized public and private semiconductor companies. The awards are celebrated at a dinner. This year's dinner is on Thursday December 12th at the Santa Clara Convention Center. The keynote speaker at the dinner is Cory Booker, the mayor of Newark NJ.

This year for the first time the Thursday of DAC is tranining day. So that would be June 6th in Austin, of course. There are four tracks of training focused on SystemC, ARM Cortex and two on SystemVerilog, all areas of increasing use in SoC design, especially in mobile.

Each track of training is divided into two parts, one held from 9am to 12.30pm, and then a second part from 2pm to 5.30pm. All sessions are taught by a professional educator from Doulos (along with an engineer from ARM for the ARM track) who is the global leader in the development and delivery of training solutions for engineers creating electronic products.

Last night at Cadence was the next installment of what I have been calling Hogan University. Jim interviewed Joe Costello about how to tell a story as part of the EDAC emerging companies series of events. The main focus was how to tell a story as a small EDA company communicating with investors, although there are obviously other forms of communication. I'm assuming that if you are reading the DAC blog that you know that Joe Costello was CEO of Cadence for many years, taking it from its birth as a merger of ECAD and SDA to a big EDA company (I think over $1B by the time he left).

Rather like in his keynote at DAC a few years ago, Joe tried to distill things down into some rules (some of them the same rules even).

This year DAC has keynotes by CEOs of two Austin-based companies Freescale Semiconductor and National Instrument. Two more keynotes (one split into two) are focused on mobile, which has become the major driver of semiconductor today. A fifth keynote, including presentation of the best paper award for DAC 2013, is by Alberto Sangiovanni-Vincentelli, who should need no introduction to readers of SemiWiki.

The core of the technical program consists of 158 peer-reviewed papers organized in 34 technical paper sessions, 20 sessions focused on EDA, 10 on embedded systems and 4 specific to system-level design. The total balance is 64% EDA papers and 34% embedded systems and system level papers. Eight papers were selected as best papers candidates.

Papers were selected from 747 submissions, with an acceptance rate of 21%. Among them two perspective papers were selected, focusing on mapping on many/multicore and reliable on-chip systems. Furthermore,  there will be 83 papers presented in dedicated poster sessions as Work in progress.

The most popular submissions topics were: Power analysis and low power design Architectures for embedded systems Physical design and design closure Test and reliability Embedded System Specification and embedded software

The first three topics are the same as last year, while this year there was an increase in interest in test and reliability and embedded systems specification and...

The last session of the day for Linley Mobile was about processors to go into smartphones. One surprise was that there is a core that nobody seems to have heard of since it is only really used in Taiwan up until now, and it is used in several Mediatek chips.

The most "glamorous" processor in a smartphone is the one in the application processor chip (or the one exposed to the apps in an integrated AP+BB chip). However there may be as many as 15 more processors in a smartphone inside things like the GPS, WiFi, power management. These processors are not automatically ARM since the code is purely internal to the chip and is not exposed to the user. It is hard for anyone to win an AP processor from ARM (although Intel is trying) since even on Android where apps are written in Java and is supposed to be portable, in reality many apps, especially games, contain ARM assembly.

The new processor that nobody had heard of is Andes Core. I was sitting next to a strategic marketing guy from Qualcomm and he'd not heard of it either. They were actually announcing a new ultra-low-power core, the Hummingbird N705, at the conference. They claim that the performance is 30% better than the ARM Cortex-M0 measured by Dhrystone MIPS/mW (although I thought the Dhrystone benchmark was regarded as obsolete these days compared to others more focused on browsing etc). They also said they had over 60 licensees, and that their development environment has over 5000 installations.

Next up were ARM. They emphasized that when it comes to the process, one size does not fit all. For the high end of the market (iPhone, Galaxy etc) ARM's roadmap is dual and quadcore Cortex A57/53. But the low end of the market is not viable in anything except premium products since 20nm and below is not a cost reduction from 28nm. So to reduce area and power and so sort of keep on Moore's law trajectory for low end requires micro-architectural innovation.

The Cortex-A7 has a very efficient power architecture with in-order 8-stage partial dual issue pipeline and integrated improved L2 cache sybsystem. It consumes less than 100mW at 1GHz (don't know what process, I'm assuming 28nm).

ARM's view on Quadcore is that although four core scales well on threaded benchmarks that these don't correlate with user-experience. Since the 3rd and 4th cores handle background and OS threads they do not need to be big. The current big.LITTLE architecture doesn't allow this, in any pair either the big core is running, or the little, but not both. However that will change soon and it will be possible to use both cores of any pair. ARM believes that this will be the most efficient way to build a Quad core (or six or eight if required for the high end) delivering energy savings of as much as 75% for the same peak performance. If a Mali GPU is added, it offloads so much of the performance needs that the high-performance graphics drivers can all run on just a little processor for power efficiency (or high FPS for the same power).

Finally, to close out the day, was Imagination who, of course, have just recently acquired MIPS. Their view is that the GPU is the heart of a smartphone. Although most of the software runs on the regular CPU (and ARM almost always), over half the die area is taken up with the GPU and it is the GPU that provides the 'wow' factor. Performance is moving towards 1 TFLOP on-chip for mobile.

Although there are lots of standard APIs, especially for graphics, the inherent architectural efficiencies remain important. Frequency, power and area all impact the user experience (or the price, which I suppose is part of the...