For 20 years (it is an anniversary year this year, have you noticed it's DAC's 50th anniversary) there has been the Electronic Design Process Symposium. It has been held each April and for the last few years at least has always been in Monterey. This year it is Thursday and Friday April 18th/19th.

The keynote on the first day is by Ivo Bolsens of Xilinx on The All-programmable SoC -- at the Heart of Next-Generation Embedded Systems. The morning is then devoted to system and platform design, with presentations from Space Codesign and Cadence, and a panel session on How to make ESL really work with Greg Wright of Alcatel, Mike McNamara of Adapt-IP, Gene Matter of Decoa Power, Guy Bois of Space Codesign, and Franck Schirrmeister of Cadence.

After lunch it is all about Design Collaboration with presentations by Synopsys, Intel, Nimbic, Xuropan and NetApp.

Next week is EDAC's annual CEO forecast panel. It is in the Doubletree in San Jose. The big guys are all here this year, Aart, Wally and Lip-Bu (isn't it great that in EDA all the CEOs just need a first name since none of them are called John or something more common). Simon Segars of ARM (not the CEO but indeed the President of ARM). This year's token startup CEO is a heavy hitter: Raul Camposano, currently CEO of Nimbic but for many years CTO (and other positions) at Synopsys. Richard Valera of Needham is the moderator.

The panel is at 7.00pm on March 14th, with a reception starting at 6pm. It is free for EDAC members (but you still have to register). $50 for anyone else (I wonder sometimes if anyone actually pays). Details are here. Registration page is here.

I used my secret powers (being a blogger will get you a press pass) to go to the first day of the SPIE conference on advanced lithography a couple of weeks ago. Everything that happens to with process nodes seems to be driven by lithography, and everything that happens in EDA is driven by semiconductor process. It is the place to find out if people believe EUV is going to be real (lots of doubt), how about e-beam, is directed self-assembly really a thing.

The keynote was by William Siegle called Contact printing to EUV and was a history and lessons learned from a career from when lithography started to the present day (well, a little bit into the future even).

The most interesting session at the Linley Tech Data Center Conference last month was the last one, on Designing Power Efficient Servers. What this was really about was whether ARM would have any success in the server market and what Intel's response might be. This is something of importance to the whole semiconductor ecosystem since, at heart, it is also about IDM versus foundry. And with Altera announcing that it would be using Intel as a foundry at 14nm the world is changing.

At the Common Platform Technology Forum there were a number of presentations by people from IBM about Silicon and Carbon Nanowires/tubes.

So what is a silicon nanowire? It is basically a FET where the active element is a wire 3-20nm in diameter. So where a FinFET has the gate wrapped around 3 sides of the transistor, a nanowire (NW) has it wrapped around all four. In essence, the wire runs through the middle of the gate.

There seem to be three issues about building a silicon nanowire. First, suspending the wire above the substrate, then depositing the gate around the wire, and controlling the shape of the wire (you'd like it to be as circular as possible). One thing you can do with NW that is new is to run several wires through the same gate, either to switch multiple signals simultaneously or to get higher current.

As you know, I've been a bit of a bear about what is happening to wafer costs at 20nm and below. At the Common Platform Technology Forum last week there were a number of people talking about this in presentations and at Harvey Jones's "fireside chat". At the press lunch I asked about this. There are obviously lots of technical issues to address to get to 10nm and below, and I don't want to underestimate them, but at some point an important question is "at what cost." Historically, with each process generation we have had something like a 50% reduction due to scaling along with a 15% increase in wafer fabrication cost resulting in an overall 35% reduction in cost per transistor. Mike Noonen of Global Foundries answered the question. But like that dog in Sherlock Holmes that didn't bark, Mike didn't say the costs are going down. He talked about the value of moving to more advanced process nodes: higher performance, lower power. This is all true, of course, and for some markets the value is enormous (smart phones and data center servers most obviously). However, we are clearly entering a new era where we don't get everything for free anymore. Nobody knows what will happen to Moore's law in practice when we don't get more transistors, faster designs, lower power designs, and it's all cheaper. Instead, it is "how much extra would you pay for lower power?". Later, Gary Patten of IBM was more explicit. "Yes," he said, "there is a cost benefit but it is much smaller that we have been used...