The last session of the day for Linley Mobile was about processors to go into smartphones. One surprise was that there is a core that nobody seems to have heard of since it is only really used in Taiwan up until now, and it is used in several Mediatek chips.

The most "glamorous" processor in a smartphone is the one in the application processor chip (or the one exposed to the apps in an integrated AP+BB chip). However there may be as many as 15 more processors in a smartphone inside things like the GPS, WiFi, power management. These processors are not automatically ARM since the code is purely internal to the chip and is not exposed to the user. It is hard for anyone to win an AP processor from ARM (although Intel is trying) since even on Android where apps are written in Java and is supposed to be portable, in reality many apps, especially games, contain ARM assembly.

The new processor that nobody had heard of is Andes Core. I was sitting next to a strategic marketing guy from Qualcomm and he'd not heard of it either. They were actually announcing a new ultra-low-power core, the Hummingbird N705, at the conference. They claim that the performance is 30% better than the ARM Cortex-M0 measured by Dhrystone MIPS/mW (although I thought the Dhrystone benchmark was regarded as obsolete these days compared to others more focused on browsing etc). They also said they had over 60 licensees, and that their development environment has over 5000 installations.

Next up were ARM. They emphasized that when it comes to the process, one size does not fit all. For the high end of the market (iPhone, Galaxy etc) ARM's roadmap is dual and quadcore Cortex A57/53. But the low end of the market is not viable in anything except premium products since 20nm and below is not a cost reduction from 28nm. So to reduce area and power and so sort of keep on Moore's law trajectory for low end requires micro-architectural innovation.

The Cortex-A7 has a very efficient power architecture with in-order 8-stage partial dual issue pipeline and integrated improved L2 cache sybsystem. It consumes less than 100mW at 1GHz (don't know what process, I'm assuming 28nm).

ARM's view on Quadcore is that although four core scales well on threaded benchmarks that these don't correlate with user-experience. Since the 3rd and 4th cores handle background and OS threads they do not need to be big. The current big.LITTLE architecture doesn't allow this, in any pair either the big core is running, or the little, but not both. However that will change soon and it will be possible to use both cores of any pair. ARM believes that this will be the most efficient way to build a Quad core (or six or eight if required for the high end) delivering energy savings of as much as 75% for the same peak performance. If a Mali GPU is added, it offloads so much of the performance needs that the high-performance graphics drivers can all run on just a little processor for power efficiency (or high FPS for the same power).

Finally, to close out the day, was Imagination who, of course, have just recently acquired MIPS. Their view is that the GPU is the heart of a smartphone. Although most of the software runs on the regular CPU (and ARM almost always), over half the die area is taken up with the GPU and it is the GPU that provides the 'wow' factor. Performance is moving towards 1 TFLOP on-chip for mobile.

Although there are lots of standard APIs, especially for graphics, the inherent architectural efficiencies remain important. Frequency, power and area all impact the user experience (or the price, which I suppose is part of the...

Of course DAC is in June. But this coming week is full of other conferences in EDA, semiconductor and neighboring spaces.

EDPS in Monterey is Thursday and Friday. The website with full details, the programme, registration etc is here.

On Wednesday and Thursday it is the Linley Mobile Microprocessor Conference in the Hyatt in Santa Clara. Full details are here.

And on Thursday at the Computer History Museum it is the GSA Technology Silicon Summit. Full details are here.

Cadence has brought a suit against Berkeley Design Automation for, as far as I can see, integrating their AFS circuit simulator with the Virtuoso Analog Design Environment (ADE) without using the (licensed) Oasis product. Since BDA is (actually was) a member of the Cadence Connections program, they have to abide by the contract which only allows them to create interfaces that their Connections legal contract allows. In particular "Member is not licensed to develop any interface to or translator for a Cadence product other than those specifically identified in exhibit x". Cadence does allow 3rd party simulators to be used with ADE but only if (a) the end-user has a license to Oasis, Cadence's integration product and (b) the integration is done through Oasis. According to the complaint, BDA have circumvented commands within Virtuoso that require the Oasis license and their integration is not through Oasis, as a result of which end-users could use AFS with ADE without obtaining an Oasis license. Cadence alleges that this is not just a breach of contract but is also a violation of the digital millennium copyright act (DMCA) and are seeking damages from BDA for loss of Oasis license fees, lost profits and so on. And, obviously, an injunction to prevent BDA from integrating AFS in this way. Per the complaint, this came to light in mid-2012 when a Cadence engineer was trying to help a common customer troubleshoot ADE/AFS issues, and the customer showed them the BDA AFS installation guide which stated that "the Oasis integration is deprecated. BDA strongly discourages users from choosing this method." The installation guide dates from 2010. Of course I have no idea of the details of what or how BDA have implemented their integration, or whether most customers using the two products together did or did not have an Oasis license anyway although Cadence believes they did not. According to a Cadence spokesperson, "Over many months before filing this lawsuit, Cadence made repeated proposals to work with BDA’s management to rectify this situation. Cadence was, however, unable to persuade BDA to comply with its contractual obligations under the Cadence Connections Program. Consequently, Cadence did not renew BDA’s participation in the Connections Program. Cadence is also seeking injunctive relief and damages for lost OASIS license fees, among other ...

UBM's EETimes and EDN today announced Kathryn Kranen as the lifetime achievement award winner for this years ACE awards program. Kathryn, of course, is the CEO of Jasper (and is also currently the chairman of EDAC). Past winners exemplify the prestige and significance of the award. Since 2005 the award was given to Gordon Moore, then the Chairman emeritus of Intel, Wilf Corrigan, the Chairman of the board of LSI, Chung-Mou Chang the Founding Chairman of TSMC and Pasquale Pistorio the honorary Chairman of ST.

As CEO of Jasper, Kathryn has taken Jasper's formal approaches to verification from a niche to a mainstream tool, managed to raise a round of funding in a very difficult environment, and put Jasper on the path to success.

This year's recipient of the Kaufman Award is Dr Chenming Hu. I can't think of a more deserving recipient. He is the father of the FinFET transistor which is clearly the most revolutionary thing to come along in semiconductor for a long time. Of course he wasn't working alone but he was the leader of the team at UC Berkeley that developed the key structures that keep power under control and so allow us to continue to scale process nodes. In the past, the Kaufman Award recipient has been finalized in the summer and actually awarded at a special dinner in the fall. This year is different. The award will take place at DAC in Austin on Sunday evening. The award will be presented by Klaus Schuegraf, Group Vice President of EUV Product Development at Cymer, Inc.

The program for EDPS in Monterey this April 18th and 19th is now available.

The first day has a keynote by Ivo Bolsens, the CTO of Xilinx, on The All Programmable SoC - At the Heart of Next Generation Embedded System. That is followed by 3 sessions on ESL & Platform, Design Collaboration, and 3D-IC.

The second day has a keynote by Daniel Nenni on The FinFET Value Proposition. This is followed by two sessions, also on FinFET. FinFET Design Challenges, and FinFET Design Enablement Challenges.

The full program is here.